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| FAN5109B -- Dual Bootstrapped 12V MOSFET Driver August 2007 FAN5109B Dual Bootstrapped 12V MOSFET Driver Features Drives N-Channel High-Side and Low-Side MOSFETs in a Synchronous Buck Configuration Enhanced Upgrade to FAN5109 Direct Interface to FAN5029/FAN5182 and Other Compatible PWM Controllers 12V High-Side and 12V Low-Side Drive Internal Adaptive Shoot-Through Protection Fast Rise and Fall Times Switching Frequency Above 500kHz OD Input for Output Disable - Allows Synchronization with PWM Controller SOIC-8 Package TTL-Compatible Logic Inputs (New) Description The FAN5109B is a dual, high-frequency MOSFET driver, specifically designed to drive N-channel power MOSFETs in a synchronous-rectified buck converter. These drivers, combined with a Fairchild multi-phase pulse-width-modulated (PWM) controller and power MOSFETs, form a complete core voltage regulator solution for advanced microprocessors. The FAN5109B drives the upper and lower MOSFET gates of a synchronous buck regulator to 12VGS. The output drivers have the capacity to efficiently switch power MOSFETs at frequencies above 500KHz. The circuit's adaptive shoot-through protection prevents both MOSFETs from conducting simultaneously. The FAN5109B is rated for operation from 0C to +85C and is available in a low-cost SOIC-8 package. Applications Multi-Phase VRM/VRD Regulators for Microprocessor Power High-Current, High-Frequency DC/DC Converters High-Power Modular Supplies General-Purpose TTL Input MOSFET Drivers Related Applications Notes Application Note AN-6003, "Shoot-through" in Synchronous Buck Converters Ordering Information Part Number FAN5109BMX Pb-Free Yes Operating Temperature Range 0C to 85C Package Packing Method Quantity Per Reel SOIC-8 Tape and Reel 2500 Note: 1. Contact a Fairchild sales representative for availability of leaded (Pb) parts. (c) 2006 Fairchild Semiconductor Corporation FAN5109B Rev. 1.0.0 www.fairchildsemi.com FAN5109B -- Dual Bootstrapped 12V MOSFET Driver Application Diagram 12V 4 VCC D1 1 BOOT Q1 CVC C PWM 2 8 HDRV SW Q2 CBOOT OD 3 Overlap Protection Circuit L1 7 VOU T COUT VCC 5 LDRV PGND 6 Figure 1. Typical Application Block Diagram V CC OD VCC BOOT PWM HDRV tFall Delay t Fall Delay VCC/3 1.2V SW 1.2V VCC LDRV GND Figure 2. Functional Block Diagram (c) 2006 Fairchild Semiconductor Corporation FAN5109B Rev. 1.0.0 www.fairchildsemi.com 2 of 14 FAN5109B -- Dual Bootstrapped 12V MOSFET Driver Pin Configuration BOOT PWM OD VCC 1 2 3 4 FAN 5009 8 7 6 5 HDRV SW PGND LDRV Figure 3. Pin Assignments Pin Definitions Pin # 1 2 3 4 5 6 7 8 Name BOOT PWM OD Description Bootstrap Supply Input. Provides voltage supply to the high-side MOSFET driver. Connect to the bootstrap capacitor (see the Applications section). PWM Signal Input. This pin accepts a logic-level PWM signal from the controller. Output Disable. When LOW, this pin disables FET switching (HDRV and LDRV are held LOW). (Also referred to as OD#.) Power Input. +12V chip bias power. Bypass with a 1F ceramic capacitor. Low-Side Gate Drive Output. Connect to the gate of low-side power MOSFET(s). Power ground. Connect directly to the source of the low-side MOSFET(s). Switch Node Input. Connect as shown in Figure 1. SW provides return for the high-side bootstrapped driver and acts as a sense point for the adaptive shoot-through protection. High-Side Gate Drive Output. Connect to the gate of high-side power MOSFET(s). VCC LDRV PGND SW HDRV (c) 2006 Fairchild Semiconductor Corporation FAN5109B Rev. 1.0.0 www.fairchildsemi.com 3 of 14 FAN5109B -- Dual Bootstrapped 12V MOSFET Driver Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Parameter VCC and LDRV to GND PWM and OD pins SW to GND BOOT to SW BOOT to GND HDRV Continuous LDRV Transient (t=200ns) (2) (2) Min. -0.3 -0.3 Max. 15.0 5.5 15.0 25.0 15.0 17.0 30.0 38.0 VBOOT+0.3 VCC VCC+0.3 VCC+2.0 Unit V V V V V V V V V V V V Continuous Transient (t=100ns, f = 500kHz) Continuous Transient (t<20ns, f = 500kHz) Continuous Transient (t=100ns, f =500kHz) (2) -1.0 -5.0 -0.3 -2.0 -0.3 VSW-1.0 -0.5 -2.0 -2.0 Transient (t<20ns, f = 500kHz) Note: 2. For transient derating beyond the levels indicated, refer to Figure 17 and Figure 18. Thermal Information Symbol TJ TSTG TL TVP TLI PD JC JA Junction Temperature Storage Temperature Lead Soldering Temperature, 10 seconds Vapor Phase, 60 seconds Infrared, 15 seconds Power Dissipation, TA = 25C Thermal Resistance, SO-8: Junction-to-Case Thermal Resistance, SO-8: Junction-to-Ambient 40 140 Parameter Min. 0 -65 Typ. Max. 150 150 300 215 220 715 Unit C C C C C mW C/W C/W Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol VCC TA TJ Parameter Supply Voltage Ambient Temperature Junction Temperature Conditions VCC to GND Min. 10.0 0 0 Typ. 12.0 Max. 13.5 85 125 Unit V C C (c) 2006 Fairchild Semiconductor Corporation FAN5109B Rev. 1.0.0 www.fairchildsemi.com 4 of 14 FAN5109B -- Dual Bootstrapped 12V MOSFET Driver Electrical Characteristics VCC and VLDRV = 12V and TA = 25C using the circuit in Figure 4, unless otherwise noted, each side. The "*" denotes specifications that apply over the full operating temperature range. Symbol Input Supply VCC ICC OD Input Parameter VCC Voltage Range VCC Current Conditions * OD = 0V Min. 6.4 Typ. 12.0 2.5 Max. 13.5 4.0 Unit V mA * VIH (OD) VIL (OD) VHYS(OD) IOD tpdl(OD) tpdh(OD) PWM Input VIH(PWM) VIL(PWM) VHYS(PWM) IIL(PWM) RHUP ISOURCE(LDRV) RHDN ISINK(HDRV) tR(HDRV) tF(HDRV) tpdh(HDRV) tpdl(HDRV) RLUP ISOURCE(LDRV) RLDN ISINK(LDRV) BGth tR(LDRV) tF(LDRV) tpdh(LDRV) tpdl(LDRV) tpdh(LDF) Input High Voltage Input Low Voltage Input Hysteresis Input Current Propagation Delay (4) * * * OD = 3.0V 2.0 0.8 250 -300 25 15 550 +300 40 30 V V mV nA ns ns V 0.8 V mV +1 2.5 2.0 1.1 2.5 25 15 40 25 2.0 40 25 55 40 2.6 1.2 1.6 30 25 30 25 1.5 3.3 A A A ns ns 550 * See Figure 5 Input High Voltage Input Low Voltage Input Hysteresis Input Current Output Resistance, Sourcing Source Current Sink Current (4) (4) * * 2.0 200 * VBOOT - VSW = 12V VDS = -10V VBOOT - VSW = 12V VDS = 10V (4,6) -1 High-Side Driver Output Resistance, Sinking Transition Times See Figure 4 See Figure 6 Propagation Delay (4,5) Low-Side Driver Output Resistance, Sourcing Source Current Sink Current (4) (4) (4) A A V ns ns ns ns ns VDS = -10V VDS = 10V 1.0 See Figure 4 See Figure 6 2.5 0.9 2.5 1.2 20 15 20 15 140 Output Resistance, Sinking Bottom Gate Threshold Transition Times (4,6) Propagation Delay (4,5) See Adaptive Gate Drive Circuit Description Notes: 3. Limits at operating temperature extremes are guaranteed by design, characterization, and statistical quality control. 4. Specifications guaranteed by design and characterization (not production tested). 5. For propagation delays, tpdh refers to low-to-high signal transition. tpdl refers to high-to-low signal transition. 6. Transition times are defined for 10% and 90% of DC values. (c) 2006 Fairchild Semiconductor Corporation FAN5109B Rev. 1.0.0 www.fairchildsemi.com 5 of 14 FAN5109B -- Dual Bootstrapped 12V MOSFET Driver Test Diagrams 12V 1 BOOT 2 PWM 3 OD 4 VCC HDRV 8 SW 7 PGND 6 LDRV 5 3000pF 3000pF 1F Figure 4. Test Circuit Figure 5. Output Disable Timing Figure 6. Adaptive Gate Drive Timing (c) 2006 Fairchild Semiconductor Corporation FAN5109B Rev. 1.0.0 www.fairchildsemi.com 6 of 14 FAN5109B -- Dual Bootstrapped 12V MOSFET Driver Typical Performance Characteristics Figure 7. Gate Drive Rise and Fall Times (1) Figure 8. Gate Drive Rise and Fall Times (2) Figure 9. HDRV Rise and Fall Times vs. CLOAD Figure 10. LDRV Rise and Fall Times vs. CLOAD Figure 11. HDRV Normalized Impedance vs. Temperature Figure 12. LDRV Normalized Impedance vs. Temperature (c) 2006 Fairchild Semiconductor Corporation FAN5109B Rev. 1.0.0 www.fairchildsemi.com 7 of 14 FAN5109B -- Dual Bootstrapped 12V MOSFET Driver Typical Performance Characteristics (Continued) 3000 12V (VCC) 12V (VCC) 2000 ID (mA) 10V 2000 ID (mA) 8V 1000 10V 8V 1000 6V 6V 0 0 5 10 0 0 5 VDS (V) 10 VDS (V) Figure 13. 3000 HDRV Pull-Up (Sourcing) Figure 14. LDRV Pull-Up (Sourcing) 12V (VCC) 10V ID (mA) 3000 12V (VCC) 10V 8V 2000 ID (mA) 8V 2000 6V 1000 6V 1000 0 0 5 VDS (V) 10 0 0 5 VDS (V) 10 Figure 15. -11 -10 -9 Vsw (V) -8 -7 -6 -5 -4 -3 0 100 HDRV Pull-Down (Sinking) Figure 16. LDRV Pull-Down (Sinking) 200 300 400 500 Transie nt Duration (ns) Figure 17. Negative SW Voltage Transient Figure 18. Negative LDRV Voltage Transient (c) 2006 Fairchild Semiconductor Corporation FAN5109B Rev. 1.0.0 www.fairchildsemi.com 8 of 14 FAN5109B -- Dual Bootstrapped 12V MOSFET Driver Typical Performance Characteristics (Continued) Figure 19. Operating Current vs. Frequency (c) 2006 Fairchild Semiconductor Corporation FAN5109B Rev. 1.0.0 www.fairchildsemi.com 9 of 14 FAN5109B -- Dual Bootstrapped 12V MOSFET Driver Circuit Description The FAN5109B is optimized for driving N-channel MOSFETs in a synchronous buck converter topology. A single PWM input signal is all that is required to properly drive the high-side and low-side MOSFETs. For a more detailed description of the FAN5109B and its features, refer to the Typical Application diagram in Figure 1 and Functional Block diagram in Figure 2. Adaptive Gate Drive Circuit The FAN5109B ensures minimum MOSFET dead-time while eliminating potential shoot-through (crossconduction) currents. It senses the state of the MOSFETs and adjusts the gate drive, adaptively, to ensure they do not conduct simultaneously. Refer to the gate drive rise and fall time waveforms shown in Figure 7 and Figure 8 for the relevant timing information. To prevent overlap during the LOW-to-HIGH switching transition (Q2 OFF to Q1 ON), the adaptive circuitry monitors the voltage at the LDRV pin. When the PWM signal goes HIGH, Q2 begins to turn OFF after a propagation delay, as defined by tpdl(LDRV) parameter. Once the LDRV pin is discharged below ~1.2V, Q1 begins to turn ON after the adaptive delay tpdh(HDRV). To preclude overlap during the HIGH-to-LOW transition (Q1 OFF to Q2 ON), the adaptive circuitry monitors the voltage at the SW pin. When the PWM signal goes LOW, Q1 begins to turn OFF after a propagation delay (tpdl(HDRV)). Once the SW pin falls below VCC/3, Q2 begins to turn ON after the adaptive delay tpdh(LDRV). Additionally, VGS of Q1 is monitored. When VGS(Q1) is discharged below ~1.2V, a secondary adaptive delay is initiated, which results in Q2 being driven ON after tpdh(LDF), regardless of the SW state. This function is implemented to ensure CBOOT is recharged after each switching cycle, particularly for cases where the power converter is sinking current and the SW voltage does not fall below the VCC/3 adaptive threshold. The secondary delay tpdh(LDF) is longer than tpdh(LDRV). Low-Side Driver ( OD = HIGH) The FAN5109B low-side driver (LDRV) is designed to drive ground-referenced, N-channel MOSFETs. The bias for LDRV is internally connected between VCC and PGND. When the driver is enabled, the driver LDRV output is 180 out of phase with the PWM input. When the FAN5109B is disabled ( OD =LOW), LDRV is held LOW. High-Side Driver ( OD = HIGH) The FAN5109B high-side driver (HDRV) is designed to drive a floating N-channel MOSFET. The bias voltage for the high-side driver is developed by a bootstrap supply circuit, consisting of an external diode and bootstrap capacitor (CBOOT). During start-up, SW is initially at PGND, allowing CBOOT to charge to VCC through the external boot diode. When the PWM input goes HIGH, HDRV begins to charge the high-side MOSFET gate (Q1). During this transition, charge is transferred from CBOOT to Q1 gate. As Q1 turns on, SW rises to VIN, forcing the BOOT pin to VIN +VC(BOOT), which provides sufficient VGS enhancement for Q1. To complete the switching cycle, Q1 is turned off by pulling HDRV to SW. CBOOT is recharged to VCC when SW falls to PGND. HDRV output is in phase with the PWM input. When the driver is disabled, the high-side gate is held LOW. OD (aka #OD) When the OD signal is HIGH, the driver is enabled and the PWM signal controls the HDRV and LDRV outputs. When the OD signal is LOW, the driver is disabled and the PWM signal is ignored. When the OD signal is LOW, both the HDRV and LDRV outputs are forced LOW to turn off both the upper and lower output FETs. (c) 2006 Fairchild Semiconductor Corporation FAN5109B Rev. 1.0.0 www.fairchildsemi.com 10 of 14 FAN5109B -- Dual Bootstrapped 12V MOSFET Driver Application Information Supply Capacitor Selection To reduce the noise and to supply the peak current, a local ceramic bypass capacitor is recommended for the supply input (VCC). Use at least a 1F, X7R or X5R capacitor. Keep this capacitor close to the VCC and PGND pins. PH(F) = PQ1 x PQ1 = RHDN RHDN + RE + RG EQ. 7 EQ. 8 1 xQ G1 x VGS(Q1) x FSW 2 where: * QG1 is total gate charge of the upper FET (Q1) for its applied VGS. As described in Equations 6 and 7, the total power consumed driving the gate is divided in proportion to the resistances in series with the MOSFET internal gate node, as shown below: BOOT Q1 RHUP RE RG Bootstrap Circuit The bootstrap circuit uses a charge storage capacitor (CBOOT) and an external diode, as shown in Figure 1. These components should be selected after the highside MOSFET has been chosen. The required capacitance is determined using the following equation: CBOOT = QG VBOOT EQ. 1 HDRV G where QG is the total gate charge of the high-side MOSFET and VBOOT is the voltage droop allowed on the high-side MOSFET drive. For example, the QG of a FDD6696 MOSFET is about 35nC at 12VGS. For an allowed droop of ~300mV, the required bootstrap capacitance is 100nF. A good quality ceramic capacitor must be used. The average diode forward current, IF(AVG), can be estimated by: IF( AVG ) = Q GATE x FSW RHDN SW S Figure 20. Driver Dissipation Model RG is the gate resistance internal to the FET. RE is the external gate drive resistor implemented in many designs. Note that the introduction of RE can reduce driver power dissipation, but excess RE may cause errors in the "adaptive gate drive" circuitry. In particular, adding RE in the low drive circuit could result in shoot through. For more information, refer to Application Note AN-6003, "Shoot-through" in Synchronous Buck Converters. EQ. 2 where FSW is the switching frequency of the controller. The peak surge current rating of the diode should be checked in-circuit, since this is dependent on the equivalent impedance of the entire bootstrap circuit, including the PCB traces. PLDRV is dissipation of the lower FET driver: PLDRV = PL(R) + PL(F) Thermal Considerations Total device dissipation: PDtot = PQ + PHDRV + PLDRV where: * PQ represents quiescent power EQ. 3 dissipation: EQ. 4 EQ. 9 where: PL(R) and PL(F) are internal dissipations for the rising and falling edges, respectively: PL(R) = PQ2 x PL(F) = PQ2 x RLUP RLUP + RE + RG RLDN RHDN + RE + RG PQ = VCC x [4mA + 0.036 (FSW - 100)] EQ. 10 * FSW is switching frequency (in kHz). * PHDRV represents internal power dissipation of the upper FET driver. * PH(R) and PH(F) are internal dissipations for the rising and falling edges, respectively: PHDRV = PH(R) + PH(F) PH(R) = PQ1 x RHUP RHUP + RE + RG EQ. 11 EQ. 12 PQ2 = 12 x Q G2 x VGS(Q2) x FSW EQ. 5 EQ. 6 (c) 2006 Fairchild Semiconductor Corporation FAN5109B Rev. 1.0.0 www.fairchildsemi.com 11 of 14 FAN5109B -- Dual Bootstrapped 12V MOSFET Driver Layout Considerations Use the following general guidelines when designing printed circuit boards (see Figure 21): Trace out the high-current paths and use short, wide (>25 mil) traces to make these connections. Connect the PGND pin as close as possible to the source of the lower MOSFET. The VCC bypass capacitor should be located as close as possible to VCC and PGND pins. Use vias to other layers where possible to maximize thermal conduction away from the IC. Figure 21. Recommended Layout for SOIC-8 Package (Not to Scale) (c) 2006 Fairchild Semiconductor Corporation FAN5109B Rev. 1.0.0 www.fairchildsemi.com 12 of 14 FAN5109B -- Dual Bootstrapped 12V MOSFET Driver Physical Dimensions Dimensions are in millimeters unless otherwise noted. Figure 22. 8-Lead SOIC Package, 0.150 (c) 2006 Fairchild Semiconductor Corporation FAN5109B Rev. 1.0.0 www.fairchildsemi.com 13 of 14 FAN5109B -- Dual Bootstrapped 12V MOSFET Driver (c) 2006 Fairchild Semiconductor Corporation FAN5109B Rev. 1.0.0 www.fairchildsemi.com 14 of 14 |
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